The manufacture of integrated circuits (ICs) in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low-k materials to avoid capacitance coupling between the metal interconnects. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD.
During a dual damascene process, there are typically four etches: via, trench, photoresist and polymer strip, and bottom barrier removal. Each has challenges irrespective of damascene strategy. For example, during the via etch, selectivity of the resist, selectivity of the bottom barrier and profile in the bottom of the via are critical. During the trench etch it is important to maintain the integrity of the bottom barrier without impacting the desired lateral dimensions of the trench. With regard to photoresist and polymer removal, the process of removing the photoresist mask, polymers and post etch residues after the features have been etched into the substrate is generally known as stripping or ashing. The stripping or ashing process should exhibit high selectivity since small deviations in the etched profiles can adversely impact device performance, yield and reliability of the final integrated circuit. Since many of the low-k dielectrics contain carbon within their structure, current processes exhibit reduced selectivity. Moreover, the current processes for ashing or stripping photoresist from new low-k ILD materials can cause damage to the material. For example, ashing can result in pullback of the dielectric film and/or cause an increase in the effective k value of the dielectric film.
In a conventional ashing process, an oxygen-containing gas is introduced into the chamber, and the RF electric power is applied to the chamber or the like to activate the gas so that it is transformed into a plasma. The gas may be an almost pure oxygen gas, an ozone gas, a mixture thereof, or a mixture of either or both of these gases with a gas such as N2, H2 and/or NH3.
To reduce damage to the low-k ILD materials caused by the ashing process, the gas pressures are often kept at a relatively low levels. Unfortunately, these ashing processes are often less effective than processes performed at higher gas pressures. As a result, ashed material may be re-deposited along the top and bottom periphery of the wafer as well as along the wafer edges. The re-deposited material can become a source of particle flaking that can adversely impact the overall IC manufacturing process.
Accordingly, it would be desirable to provide a method and apparatus for removing such re-deposited ashed materials that accumulate on a semiconductor wafer.